Introduction
The high-luminosity large hadron collider (HL-LHC) [1] at CERN is designed to produce up to a tenfold increase in the rate of proton–proton (pp) collisions compared to the LHC, producing up to 200 simultaneous pp collisions for every bunch crossing. The increased luminosity will permit further scientific studies of fundamental particle physics, such as the Higgs Boson [2], [3], [4]. The tenfold increase in collision rates requires the development of new readout electronics [5] for the ATLAS [6] liquid argon (LAr) calorimeter system.
The HL-LHC LAr readout architecture requires the development of a full-custom 8-channel ADC [7], [8], [9] to digitize each calorimeter channel at the HL-LHC bunch crossing frequency of 40 MHz. Designing a suitable ADC for this purpose imposes stringent analog accuracy, reliability, scalability, and system integration requirements that are both specific to the HL-LHC and not trivial to meet. Hence, there exist relatively few prior examples in the literature. The split-SAR ADC topology [10] has been investigated and a custom, pipelined ADC [11] has been used in similar applications but they do not meet scalability and radiation hardening requirements for the LAr readout upgrade.
In this article, we present an 8-channel, radiation-hardenedby- design (RHBD), 15-bit resolution, 14.2-bit (85.5-dB) dynamic range, 11.4-ENOB (70.3-dB SNDR), 40-MSPSADC data acquisition system for the ATLAS LAr HL-LHC upgrade. An overview of the readout architecture is provided in Section II. The system and ADC requirements are summarized in Section III. The ADC architecture selection is discussed in Section IV, followed by circuit-level implementation details in Sections V and VI. Experimental results, including measurements of analog performance and radiation tolerance, are presented in Section VII, followed by comparison and conclusions in Sections VIII and IX.
Overview of Atlas Lar HL-LHC Readout
The HL-LHC LAr readout signal path is shown schematically in Fig. 1. The ATLAS LAr calorimeter measures the energies of particles produced in the collisions in the HL-LHC. Particles traversing any of the 182468 calorimeter cells ionize the LAr medium, resulting in triangular pulses of electrical current being produced. These pulses are transmitted out of the LAr cryostat by cables which are terminated on so-called Frontend Boards (FEB2) [5], [9], [12] being developed for the HL-LHC that reside in crates mounted directly on the cryostat feedthroughs. Each FEB2 reads out 128 calorimeter channels on two gain scales, requiring 256 independent ADC channels, implemented via 32 ADC ASICs of eight independent ADC channels each. The three custom ASICs in the signal chain are depicted in Fig. 1 (preamplifier/shaper, this 8-channel ADC, and data aggregator) with supporting electronics mounted on the front-end boards. Power to the FEB2 is input at 48 V and distributed using on-board, radiation-hardened dc-dc converters and low-dropout regulators. The FEB2 boards are water-cooled to operate approximately at room temperature.
Simplified readout signal flow of the ATLAS LAr calorimeter with emphasis on the analog signal chain.
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The custom “ALFE” preamplifier/shaper (PA/S) ASIC [13] shown in Fig. 1 terminates the signal cables, amplifies the current pulses and converts them to voltage, splits each signal into two overlapping linear gain scales (dubbed “high-gain” [HG] and “low-gain” [LG], with a gain ratio ~25 V/V), and applies shaping and analog matched filtering with an CR-RC2 filter for improved SNR [14]. Data from both gain scales are processed off-detector and HG data is used if it has not saturated. To minimize interchannel cross-talk and due to constraints from the FEB2 layout, an unterminated transmission line of length ~20 cm exists between the PA/S outputs and ADC inputs. To avoid halving the signal dynamic range, this line cannot be terminated, so the ADC must address its own sampling kickback interacting with the unterminated line.
The conditioned signals are quantized by the “COLUTA” 8-channel ADC ASIC discussed here. The signals are quantized at a rate of 40 MSPS which is synchronous to the rate of pp collisions in the HL-LHC. To achieve the required performance, the ADC incorporates an on-chip digital data processing unit (DDPU) to apply calibrated bit weights to the quantized signals. The DDPU also formats each digitized sample into a 16-bit word, which is then serialized, timestamped, and transmitted at 640 Mb/s using the CERN low-power signaling (CLPS) specification [15]. Timestamping ensures all samples from all ADC channels are synchronous with each other. Each ADC ASIC outputs ten 640 Mb/s serial lanes, one for each ADC channel plus two for timestamp metadata.
The digital data from one FEB2 with 32 ADC ASICs (320 serial lanes, each at 640 Mb/s) are aggregated and packetized to multiple 10 Gb/s streams using the custom “low-power gigabit transceiver” (lpGBT) ASIC [16], [17], before being transmitted off-detector via 22 10-Gb/s optical links. Two additional lpGBT ASICs on each FEB2 also provide redundant clock and control signals. A low-jitter, 50% duty cycle 40 MHz and a nonprecision 640-MHz clock are distributed on the FEB2 for use as a precision sampling clock and for data serialization purposes, respectively. I2C networks are used to configure all the various ASICs. The digital data undergoes further matched filtering and correlation, depending on specific scientific goals.
ADC Requirements
As described below, the ADC requirements are driven by the LAr calorimeter performance, the scientific goals of the HL-LHC program, and the HL-LHC experimental environment. We define resolution to be the full-scale input over the VLSB , and dynamic range to be the full-scale rms over the ADC noise rms.
A. Analog Accuracy
The raw unipolar LAr pulse before shaping and matched filtering and the bipolar LAr pulse after the PA/S are shown in Fig. 2. The unipolar LAr pulse before the PA/S is difficult to quantify with adequate SNR. The positive and negative amplitudes of the shaped LAr pulse are proportional to the positive amplitude of the unipolar raw LAr pulse waveform. Each pulse is the signature of a subatomic particle interaction within the calorimeter. The rate of such pulses is proportional to the rate of pp collisions, and the amplitude is proportional to the energy deposited in an individual calorimeter cell by the interacting particle. The shaper’s response is analytically known. The spectral content of the shaped LAr pulses predominantly reside between 5 and 8 MHz, because the chosen shaper filter’s time constant is a design tradeoff between the so-called pileup noise [14] and the 40-MSPS sampling rate which is synchronous to the accelerator beam structure.
Raw unipolar LAr pulseshape before and the resulting bipolar waveform after preamplification and shaping, with arbitrary normalization. The sampling points for the ADC are spaced 25 ns apart.
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The quantization requirements are summarized in Fig. 3 where the intrinsic measurement uncertainty of the calorimeter relative to the energy of the particle being measured, (σ(E)/E) , is used to determine linearity and SNDR requirements for the ADC [18], [19]. This is done by setting (σ(E)/E)−1 equal to S/(N+D) , where S is the signal power of interest and N+D are noise and distortion powers of the quantizer. Full-scale of the PA/S output and the quantizer input is defined to be 2 Vpp differential. According to the detector specification in Fig. 3, a single quantizer with at least 94.1 dB (about 16 bits) of dynamic range and 43.5 dB of SNDR would be required to quantize the calorimeter signal without significantly degrading its signal fidelity [5].
Meeting these specifications with a single quantizer, while satisfying reliability and radiation-hardening requirements, is difficult. Instead, the requirement has been relaxed at the system level by splitting each LAr calorimeter channel into two overlapping gain scales that are simultaneously digitized with two independent ADC channels. Hence, the 182468 calorimeter channels require 364936 ADC channels. The high-gain (HG) channel has a 25× V/V amplification built into the PA/S, whereas the low-gain (LG) channel is unity gain, allowing the total 16-bit dynamic range to be covered using two ADCs. Scale errors between ADC channels are handled at the system level. HG and LG performance is plotted in Fig. 3, assuming that both channels are quantized using an ADC with 14 bits of dynamic range and 12 ENOB at full-scale, though there is sufficient margin to tolerate a performance of ≥11 ENOB. The single-quantizer specification of 16-bit dynamic range is thus relaxed to 14 bits under the HG/LG scheme, with design margin built in.
B. Reliability and Radiation Tolerance
Due to their on-detector location, the FEB2 boards experience significant radiation exposure due to particles resulting from the collisions, and cannot be reasonably shielded from this radiation. The FEB2 boards are also inaccessible during operation and can be accessed for maintenance at most once per year. Furthermore, the HL-LHC is expected to operate for at least 12 years [20], with minimal downtime, in order to maximize its scientific output. Therefore, the 364936 ADC channels must be “install-and-forget” and operate reliably for extended periods in harsh conditions.
The ADC must be RHBD, maintaining performance while withstanding (including some safety factors) a total ionizing dose (TID) of at least 1.4 kGy(Si), sustain 4.1×1013 neq/cm2 nonionizing energy loss (NIEL), and tolerate 1.0×1013 hadrons/cm2 capable of producing single-event upsets (SEUs) [5] over the 12-year operating lifetime. Such radiation dose rates are typically encountered by satellites in geostationary orbit [21].
Transient errors affecting one or a few data samples due to SEUs can be tolerated and corrected by offline data analysis since the LAr pulse shape is analytically known. However, persistent errors affecting many consecutive samples or failure mechanisms that require power cycling would incur downtime and cannot be tolerated. To minimize off-chip active components and their potential radiation vulnerability, all necessary functionalities are integrated on-chip and the ADC is integrated seamlessly between the PA/S and lpGBT ASICs.
C. Calibration
Achieving the required analog performance requires determining and applying calibration constants to the ADC bits. The precise understanding of the detector response required to extract the best physics results relies on stable conditions, including calibration, over extended periods of data collection.
This requirement disfavors the use of background calibration schemes. In addition, any background calibration scheme that depends on the signal being quantized would be challenging since the LAr pulse shape is nonsinusoidal with a variable occurrence rate. In addition, the associated logic overhead is unfeasible to implement in the radiation environment. As a result of these considerations, foreground calibration is preferred, at the expense of some downtime to periodically calibrate all ADC channels. The foreground calibration could be performed between HL-LHC runs, during the operational downtime when new beams are being prepared.
Given the total volume of LAr readout data, which exceeds 300 Tb/s, it is essential for the calibration constants to be stored and applied on-chip by the DDPU embedded in each ADC channel. Therefore, all calibration hardware must be RHBD to avoid erroneous calibration parameters, for example, caused by SEUs, that would invalidate data. The calibration constants would be downloaded at the beginning of each HL-LHC run, which typically lasts of order one day.
D. Summary
The ATLAS LAr calorimeter presents a unique set of performance, reliability, and scalability engineering challenges [5]. The increased luminosity of the HL-LHC imposes more stringent analog performance and radiation robustness requirements on the front-end readout electronics that directly interface with the detector. The calorimeter readout requires 364936 independent ADC channels, each quantizing at a rate of 40 MSPS with ≥14 bits (84 dB) of dynamic range, ≥11 ENOB (68-dB SNDR) of linearity, and full-scale defined to be 2 Vpp differential. The 40-MSPS sampling rate is set by the bunch crossing rate of energetic particles in the HL-LHC and is synchronized to the broader HL-LHC infrastructure. The ADC must be RHBD and radiation-induced failure mechanisms must be transient in nature, cannot require a power cycle for upset recovery, and performance degradation must not be excessive. Foreground calibration must be implemented on-chip for each channel, eight independent channels must be integrated onto a single chip, and the ADC must seamlessly interface with the PA/S and data aggregator ASICs.
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